1. Field of the Invention
The present invention relates to a semiconductor memory device and, in particular, to a configuration of a semiconductor memory device for testing the semiconductor memory device at high speed.
2. Description of the Background Art
As the memory capacity of semiconductor memory devices and, in particular, of dynamic RAMs (referred to as DRAMs hereinafter) is greatly increased, the time required for semiconductor memory device testing is also greatly increased.
As the memory capacity of a semiconductor memory device is increased, the number of word lines included therein is also increased. Thus, the time required for performing operations of writing and reading information into and from memory cells while sequentially selecting word lines is significantly increased and thus the problem of the time increased for semiconductor memory device testing is caused.
The problem described above is severe in process testing such as burn-in testing. In the burn-in testing, a semiconductor memory device is operated at high temperature and high voltage so that latent initial defections such as defections of a gate insulating film, an interlayer insulating film between interconnections and of interconnections of an MOS transistor as a component, defections resulting from particles mixed during the manufacturing process and the like may be revealed to remove defective products before shipping.
Such a burn-in testing is a testing essential to maintaining the quality of products to be shipped and thus increase in the time required for the testing is directly linked to increase in cost for manufacturing semiconductor memory devices.
The problem of the increased testing time is also caused in reliability testing such as lifetime testing.
In a burn-in testing such as described above, a predetermined information to be stored is prewritten into each memory cell which is sequentially read by sequentially selecting a word line and the read information is compared with an expected value, which is the written information, to detect any data bit error and thus find any defection of a product. Thus, such a burn-in testing is typically conducted on each semiconductor memory device after chip separation and assembling so that a predetermined information to be stored is externally written into a memory cell at a predetermined address. More specifically, a burn-in testing such as described above is conducted, for example, on a semiconductor memory device which has been sealed into a mold package and assembled into a shape similar to the final product.
For DRAM or the like, a physical address corresponding to the actual arrangement of a memory cell on a semiconductor memory device can not always match an externally applied address value depending on the arrangement memory cells, word lines and pairs of bit lines.
Writing of data into a semiconductor memory device which requires address scrambling, in particular, writing of data in a checker pattern is elucidated.
FIG. 28 is a schematic block diagram showing a configuration of a circuitry for writing data in a conventional DRAM 2000.
The conventional DRAM 2000 includes a memory cell array 100 having memory cells arranged in a matrix, a row decoder 102 which selects a corresponding word line (a corresponding row) in response to a row address signal externally applied, a column decoder 104 which selects a corresponding pair of bit lines (a column) in response to a column address signal externally applied, a control circuit 118 which receives a row address strobe signal RAS and a column address strobe signal /CAS both externally applied to output an internal control signal, a write control circuit 136 which is controlled by control circuit 118 and also receives an externally applied write enable signal /WE to control writing operation, a data input buffer 162 which receives, buffers and outputs external write data ext.DQ0-ext.DQn input to an external data input/output terminal 160, and a write driver circuit 164 which is controlled by write control circuit 136 and also receives an output from data input buffer 162 to drive the potential level of an selected pair of bit lines to a potential level depending on the write data.
Signal /WE input to external control signal input terminal 154 is a write enable signal which designates data writing. Signal /RAS input to external control signal input terminal 152 is a row address strobe signal which initiates an internal operation of a semiconductor memory device and also determines an active time period of the internal operation.
When signal /RAS is activated, the circuit which is related to the operation for selecting a row of memory cell array 100, such as row decoder 102, is activated. Signal /CAS input to external control signal input terminal 150 is a column address strobe signal and activates the circuit for selecting a column in memory cell array 100.
FIG. 29 is a conceptual view showing a correspondence between a row address externally applied and an internal row address signal in a memory cell.
In the example shown in FIG. 29, address scrambling is performed for recombination for A0R and A1R of a row address signal externally applied.
An exclusive OR circuit 142 receives the second least significant bit signal A1R and the third least significant bit signal A2R of an externally applied row address signal and outputs the second least significant bit signal RA1 of an internal row address signal.
An external OR circuit 140 receives the least significant bit A0R of the externally applied row address signal and also exclusively receives an output of exclusive OR circuit 142 to output the least significant bit signal RA0 of the internal row address signal.
Generally, depending on the arrangement of word lines, bit lines and the like, an externally applied address and a physical address of a memory cell selected on memory cell array 100 has a correspondence equivalent to execution of some logical processing.
Such a recombination between an externally applied address signal and an address signal selected in internally writing data causes a problem such as described below.
Prior to describing the problem, a structure of a memory cell portion in a typical DRAM will be briefly described.
FIG. 30 is a cross sectional view of the structure of the memory cell portion of the typical DRAM. Referring to FIG. 30, a DRAM memory cell 614 includes a memory cell transistor formed of an n type heavily doped layer 606 to which bit line 611 is connected, a word line 605 and of an n type heavily doped layer 606 to which a storage node 609 is connected, and a memory cell capacitor formed of storage node 609 for storing electric charge therein, a dielectric film 615 and of a cell plate 610 which is an opposing electrode of the capacitor. Each element is separated by a separating oxide film 604, and formed closer to the substrate are a p type well 603 and an n type well 602 on substrate 1. P type well 603 receives potential supply from an interconnection 613 via the p type high concentration layer to fix its potential.
FIG. 31 is an equivalent circuit diagram of the memory cell portion shown in FIG. 30. Referring to FIG. 31, storage node 609 as an accumulated charge capacitor electrode of the memory cell is connected to p well 603 by a diode configuration.
Now it is assumed that there is leak current between the memory cell capacitors of adjacent memory cells or that there is a latent defection which will cause such leakage.
In order to detect whether there is such defective leakage, the potential levels of two adjacent storage nodes 609 need only be held at those different from each other, for example, high (H) level and low (L) level. Thus, if there is leakage between memory cells, a read data will be read as defective data which is different from an expected value. Also, application of voltage stress allows any latent defection between the adjacent memory cells to appear as the time period during which the stress is applied is increased.
FIG. 32 is a conceptual view of a two-dimensional data arrangement when data of potential levels different from each other are written into physically adjacent memory cells.
In FIG. 32, 2K (accurately, 2048) memory cells are arranged in the X direction (the row direction).
When data the potential levels of which are different from each other are written into physically adjacent memory cells, as described above, the pattern of written data will be ultimately a pattern of a so-called checker flag (referred to as a checker pattern hereinafter). More specifically, L and H levels are written corresponding to black and white squares the checker flag, respectively.
In order to externally write data in such a checker pattern, however, the correspondence between an address externally applied and an internal address need be taken into consideration beforehand in externally applying the address signal, since a recombination is performed between an externally applied row address signal and an internal address actually selected in DRAM 2000, as described above.
Furthermore, in writing data in such a checker pattern as shown in FIG. 32, effects of address signal scrambling as well as effects of data scrambling as described below need be taken into consideration.
FIG. 33 is a circuit diagram showing a configuration of a pair of bit lines, word lines and memory cells corresponding to a specific column in memory cell array 100, and sense amplifier connected to the pair of bit lines.
It is assumed that there are n+1 word lines WL to which numbers 0-n are allocated in order.
A memory cell is connected corresponding to an intersection of a pair of bit lines BL and /BL and a word line WL. Each memory cell includes a memory cell capacitor MC which receives a cell plate potential at one end, and a memory cell transistor MT connected between the other end of memory cell capacitor MC and a corresponding bit line and having its gate connected to a corresponding word line WL. A memory cell the word line WL number for which is an even number is connected to bit line BL, and a memory cell the word line WL number for which is an odd number is connected to bit line /BL.
Thus, if an H level is written into all of the memory cells, for example, a potential level to be applied to the pair of bit lines BL and /BL will be different depending on whether each memory cell is connected to a word line WL of an even or odd number.
FIG. 34 schematically shows a correlation between data to be written into, that is, a potential level to be applied to bit line BL in writing data into such a memory cell and a potential level output on bit line BL in reading data from the memory cell. As described above, a potential level applied to bit line BL differs even in writing same data depending on whether a memory cell into which the data is to be written is connected to a word line (a row) of an even or odd number.
Hereinafter, /.eta. represents a logic operation which determines a potential level (a logic level) to be applied to bit line BL for write data Din externally applied, wherein / represents an inverted operation of an logic operation and thus an operation /.eta. represents an inverted logic operation of an operation .eta..
Referring to FIG. 34, logic operation /.eta. corresponds to an exclusive OR operation of the least significant bit A0R of a physical address of word line WL and write data Din. More specifically, when the least significant bit A0R of a physical address attains an L level, that is when it corresponds to a word line of an even number, write data Din externally applied passes through an exclusive logic OR operation circuit 144 receiving signals A0R and Din and is transparently applied to a memory cell. In contrast, when signal A0R attains an H level, that is, when it corresponds to a word line of an odd number, write data Din is inverted by exclusive OR operation circuit 144 and thus applied to the memory cell.
In reading data, an output of an exclusive OR operation circuit 146 which receives both data output from the memory cell and signal A0R is entirely similarly output as read data Dout.
FIG. 35 is a schematic block diagram showing a process of address scramble and written data scramble in data writing.
In FIG. 35, /.phi. represents a logic operation for such a conversion of a physical address into an internal address as shown in FIG. 28.
A logic operation /.phi. is applied to A0-Ai input to an external address input terminal 110, which are then input to memory cell 100. Meanwhile, a logic operation /.eta. is applied to written data Din input to data input terminal 160, which is then applied to the memory cell.
In fact, a circuit for performing such an operation /.phi. or /.eta. does not exist, and arranging of word lines and bit lines merely bring about a result equivalent to the execution of such an operation. Hereinafter, however, in order to simplify the description, it is assumed that such operations are applied to externally applied address signals A0-Ai and externally applied written data Din to select a memory cell, write data and the like.
As described above, in writing data into a selected memory cell, a recombination operation is equivalently performed with a predetermined correspondence between an externally applied address signal and physical address actually selected on a memory cell array. Furthermore, with respect to writing data itself, a result of execution of a predetermined logic operation is equivalently written into the selected memory cell. Thus, in order to write data in such a checker pattern as shown in FIG. 32 into the memory cell array by externally applying an address signal and written data, it is necessary to take it into consideration that logic operations /.phi. and /.eta. are internally performed, preperform inverted versions thereof, that is, preperform operation .phi. for an address signal and operation .eta. for written data and to perform operation /.phi. for the address signal and operation /.eta. for the written data within DRAM 2000 so that desired data is written into a desired memory cell.
More specifically, it is necessary to prepare an inherent software for writing data depending on the configuration of a DRAM.
In burn-in testing or the like, conventionally a semiconductor memory device of interest is connected to a tester and a reading/writing processing of data is performed per memory cell.
In this case, the tester includes a fail bit map and a test result for each memory cell such as fail/pass is recorded at a corresponding bit on the fail bit map.
Furthermore, the tester is mounted with a software which address-scrambles the value of an address to be supplied, depending on address mapping of a semiconductor memory device to be tested. Such a function of the software allows the test result of each memory cell described above to be recorded on the above fail bit map not at a bit corresponding to an address value based on the address decode logic of the semiconductor memory device but at a bit located at a physically corresponding position. This allows the physical location of any defective bit on a memory cell array to be specified through analysis of the above fail bit map. For example, a cause of defection such as interference between memory cells can be elucidated.
For a conventional technique in which address scrambling is performed in the tester using a software, however, specifying and analyzing the location of a defective bit has the following problems.
Firstly, a software need be prepared which corresponds to the address mapping of a memory cell array. More specifically, if a semiconductor memory device to be tested has different function and configuration, the physical arrangement order of each memory cell and the address mapping defined according to the decode logic are also different. Thus, a software is required which is provided with a logic of address scrambling corresponding to a semiconductor memory device for each address mapping inherent to the semiconductor memory device.
Secondly, address scrambling which can be achieved using a software is limited depending on the processing capability of the tester. For example, when a semiconductor memory device with a complex address arrangement such as hierarchical address mapping configuration is tested, the software for address scrambling is complicated. Thus, processing capability is insufficient depending on the specification of a tester and semiconductor memory device testing for evaluation may not be able to be conducted.
Thirdly, in burn-in testing or the like, data in a so-called checker pattern is written into a memory cells arranged in a matrix so that any initial defection due to leakage current between memory cells is revealed, as described above. More specifically, an H level and an L level in two dimension are alternately written into physically adjacent memory cells. This allows voltage stress to be applied between the physically adjacent memory cells.
It is necessary in writing such a checker pattern into memory cells, however, to independently develop a software for performing such data writing for each semiconductor memory device, taking into consideration the address scrambling mentioned above.
Furthermore, other than the problem of the software on the tester side with the necessity of the address scrambling described above, there also is the problem described below.
A conventional burn-in testing is conducted on semiconductor memory devices after the final assembling process such as mold packaging is completed. However, a semiconductor memory device in which some initial defection has been found in burn-in testing is not shipped as a product and thus the manufacturing cost for assembling for such a chip is wasted.
If burn-in testing is conducted on a wafer, for example, and any defective chip can thus be revealed and be removed prior to assembling process, such a manufacturing cost can be reduced.
It is necessary in burn-in testing a semiconductor memory device chip in the form of a wafer, however, to typically apply an address signal or a control signal and written data and the like for each chip and carry out testing with a considerable number of probe needles in contact with each chip.
However, the contact of such probe needles with each chip over the entire surface of a wafer is physically difficult to achieve and furthermore the tester side is extremely burdened with performance of such parallel testing.